module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);

    parameter S0 = 3'b000;
    parameter S1 = 3'b001;
    parameter S2 = 3'b010;
    parameter S3 = 3'b011;
    parameter S4 = 3'b100;
    
    always @(*) begin
        case(y)
            S0:	Y0 = x ? S1 : S0;
            S1:	Y0 = x ? S4 : S1;
            S2:	Y0 = x ? S1 : S2;
            S3:	Y0 = x ? S2 : S1;
            S4:	Y0 = x ? S4 : S3;
        endcase
    end
    
    assign z = (y == S3) || (y == S4);
    
endmodule
